Design of a code converter

Logic Design  Laboratory Grade Sheet

This page is to be submitted with the A section completely filled out. Do not include your circuit number or Input/Output BCD code in the heading

1. (This section to be completed by student)

Student logic number:                                       

Student name: (Last)      ___________________, (first) _________________________

Experiment number:                   2                        

Date/time:    ______/_____/ _______,  __________a.m./p.m.

1. Preliminary checking
2. Is the report written on 8½” x 11” paper and stapled at left margin?
3. Is a cover page included?
4. Is the report written using the given template?
5. Circuit Template is included (with name and student logic number on label)?
6. Is the correct assignment used in design?

Report will not be accepted if the answer is “NO” to any of the above questions.

1. Grade
2. Design procedures: supporting theory, details, etc. (25) ___________
3. Is design correct? (50) ___________
4. Minimization of design (15) ___________
5. List of ICs and unused gates (10) ___________

Gross grade           (100)  __________

1. Adjustment to gross grade
2. Cover page, folder, disk (-5)  ___________
3. Title box of schematic diagram (-5)  ___________
4. Schematic diagram in correct format (-10) ___________
5. Misrepresentation of test (simulation) results (-30) ___________
6. Neatness and legibility (-10)  __________
7. Templates (-20)  __________

Final grade            (100)  __________

Comments:  ___________________________________________________________________________

_____________________________________________________________________________________

Grader: _________________________                                                            Date: ____/____/________

Report will be graded based on a maximum of 50 (out of 100 points) if a schematic diagram is not received within three calendar days of notification or re-submitted schematic file still cannot be opened or is not readable.

Grade: ___________

Experiment 2   Design of a Code Converter

1. Input and output code assignment

Input code:            ____________________     

Output code:         ____________________

Do not change code once assigned. Your TA will keep a record of your assigned code and will only grade your report if the correct assigned code is used. For example, decimal digit 4 for the (5, 4, 2,-1) weighted code is (1001), you cannot change it to (0100) which is listed as an invalid code. The reason that I won’t allow this is that by using 0100 instead of 1001, the K-maps for the outputs may become very simple and you will not learn what I want you to learn from the assignment.

2. Design Procedures

Truth table for code converter (If ABCD is an invalid input code,

write “invalid” in the column for decimal digits.)

Express V, W, X, Y, Z in minterm list form

V   = S m(

W = S m(

X   = S m(

Y   = S m(

Z    = S m(

 Design for V

K-map for V

Suggestion: In making the minterm lists for V, W, X, Y, Z you need to differentiate between the decimal equivalence of the binary input combination of A,B,C,D and the representation of a binary code for a decimal digit. To avoid confusion, remove the left most column of the table in Section 1 before writing the miniterm lists for the output functions. Also, remember to include the don’t-care terms for W, X, Y, Z.

Realization and gate transformation for V

Minimize either the simplest SOP or the simplest POS obtained from the K-map to an expression with a minimum number of literals.

V =

Draw the circuit for V with a minimum number of 2-input AND gates and 2-input OR gates using LogicWorks:

Draw the circuit for V with only NAND gates and/or NOR gates using LogicWorks:

Design for W

K-map for W

Realization and gate transformation for W

Minimize either the simplest SOP or the simplest POS obtained from the K-map to an expression with a minimum number of literals.

W =

Draw the circuit for W with a minimum number of 2-input AND gates and 2-input OR gates using LogicWorks:

Draw the circuit for W with only NAND gates and/or NOR gates using LogicWorks:

Design for X

K-map for X

Realization and gate transformation for X

Minimize either the simplest SOP or the simplest POS obtained from the K-map to an expression with a minimum number of literals.

X =

Draw the circuit for W with a minimum number of 2-input AND gates and 2-input OR gates using LogicWorks:

Draw the circuit for X with only NAND gates and/or NOR gates using LogicWorks:

Design for Y

K-map for W

Realization and gate transformation for Y

Minimize either the simplest SOP or the simplest POS obtained from the K-map to an expression with a minimum number of literals.

Y =

Draw the circuit for Y with a minimum number of 2-input AND gates and 2-input OR gates using LogicWorks:

Draw the circuit for Y with only NAND gates and/or NOR gates using LogicWorks:

Design for Z

K-map for Z

Realization and gate transformation for Z

Minimize either the simplest SOP or the simplest POS obtained from the K-map to an expression with a minimum number of literals.

Z =

Draw the circuit for Z with a minimum number of 2-input AND gates and 2-input OR gates using LogicWorks:

Draw the circuit for Z with only NAND gates and/or NOR gates using LogicWorks:

4. List of ICs and unused gates

In all of your designs, strive to minimize cost, as much as possible, by minimizing the number of chips (because a chip is more expensive than a gate).

Make judicious use of 7400 or 7402 to get A’, B’, C’, D’ because the proper choice of what to use may help you with improving your design (i.e., minimizing the number of chips), because there may be spare (unused) gates in some of the chips.

5.   Simulation results

Table for simulation results

(Place a check mark in the column “Incorrect results” for each simulation value that is different from the value listed  in the truth table in Section 2.)

Last Updated on February 11, 2019