Arithmetic Logic Unit Design

Arithmetic Logic Unit Design

In this assignment you will learn how to design a complete system in Verilog using top-down approach. You will also learn how to use modular programming and build top modules in Verilog by instantiating different modules.

Overview:

In this assignment you will use Verilog to design a 4-bit ALU using top-down approach. You will be building the ALU using 4 1-bit adder/subtractor units and other gates.

Part 1: 1-bit Adder/subtractor

In this part you will be designing a single logic circuit that can serve as both a 1-bit adder and a 1-bit subtractor. The adder will include the following signals, as shown in figure 1 below:

Inputs: A, B: 2 one-bit numbers to be added or subtracted, Cin: carry in into the adder, and E: an input signal to control the operation, when E=0, the Adder will add, when E=1 the Adder will subtract.

Outputs: S: the result sum/difference, and Cout: The Carry bit.

Figure 1

Procedure:

Start by designing the whole circuit on paper and develop all Boolean equations or circuit diagrams.
Create a new project “ALU” in Quartus.
Create a new Verilog module (Adder.v) with 4 inputs and 2 outputs as shown figure 1.
Use Structural Modeling ONLY to describe the circuit.
Compile and synthesize the code and correct any errors.
Create a test bench to test the module, use all possible inputs to plot the simulations schematics

Deliverables for part 1 ONLY:
page1image15520

Upload one pdf file containing the following items:

a. A snapshot of the schematic, make sure the inputs and outputs signals are all clear and showing.

b. The schematic of your design, use any CAD tools of your choice. Identify all inputs and outputs clearly in your diagram.

c. A snapshot of the RTL diagram in Quartus.

Part 2: 4-bits Adder and Subtractor

In this part of the assignment, you will be creating a 4-bit adder using 4 instances of the 1-bit adder from part 1, as shown in figure 2.

Figure 2

Create a new module Adder4 with the following signals:
Inputs: A (4 bits), B (4 bits), E (one-bit).
Output: S (4-bits), Carry (one-bit), Overflow (1-bit).
Using the adder from part 1, write structural Verilog code to create the 4-bit adder.
Compile and synthesize the code and correct any errors.
Create a test bench to test for at least 10 different inputs. Your test bench should cover cases toconvince a reasonable person that the adder/subtractor is working properly.

Deliverables for Part 2 ONLY:

Upload one pdf file containing the following items:
page2image11936

The simulation results, make sure all inputs and outputs are clear and readable. All inputs and outputs should be displayed in Decimal.
The RTL design from Quartus.
A snapshot of your test bench.
A snapshot of your Verilog code.

Part 3: ALU

In this part of the assignment, you will be building a 4-bit ALU using the adder you designed in part 2 and other components. The block diagram for the 4-bit ALU is shown in Figure 3.

Figure 3

Design procedure:

Design an 4-bit ALU using the adder you designed in step 2 to add and subtract. Inputs to the 4-bits ALU is two 4-bit numbers A and B, and a 3-bits Control signal ALUOp ONLY. The outputs are:ALUResult, C, Z, N and V, where C is a carry out flag, Z is the zero flag, N is the negative flag, and V is an overflow flag, see figure 1.

The ALU will be performing the functions in Table 1:

Control
page3image10152page3image10320

The SLT function performs a comparison between A and B by computing A-B. If A is less than B, Result will equal 1 otherwise it equals 0.
Create a test bench to test the functionality of your ALU.
Build a self-checking testbech to test the 4-bit ALU in Quartus only. It is prudent to think through a set of input vectors. Develop an appropriate set of test vectors to convince a reasonable person that your design is correct. Complete Table 2 below to verify that all 5 ALU operations work as they are supposed to. Note that the values are expressed inhexadecimal to reduce the amount of writing. Follow the instructions from class to create the test bench using the data in the table.Table 2

Test (hex)

F[2:0] page4image12192page4image12616

A (hex)
page4image14056

B (hex)
page4image15304

Y (hex)

N
page4image18104page4image18528

V
page4image19736

Z

C
page4image22760

ADD 0+0

2
page4image25360page4image25784

0
page4image26848

0

0

0
page4image29712page4image30136

0

1

0
page4image33000

ADD 0+(-1)

2

0

F

F

1

0

0

0

ADD 1+(-1)

2
page4image43296page4image43720

1
page4image45120

F
page4image46328

0

0
page4image49088page4image49512

0
page4image50720

1

0
page4image53480

ADD F+1

2
page4image56080page4image56504

F
page4image57568

1
page4image59520page4image59944 page4image61440

SUB 0-0

SUB 0-(-1)
page4image66376page4image66800 page4image67568 page4image68904page4image69328 page4image70824

SUB 1-1
page4image74880 page4image76800

SUB 0-1
page4image82928 page4image85952

SLT 0,0

SLT 0,1

SLT 0, -1
page4image102744 page4image103224 page4image105768 page4image106248

SLT 1, 0

SLT -1,0

AND F, F
page4image122600 page4image123080 page4image125624 page4image126104

AND F, 2

AND 2, 7

AND 0, F

OR F, F

OR 2, 7

OR 0, F

OR 0, 0

Deliverables for part 3 only:

Combine all deliverables into one pdf file before submitting. Do not submit zipped folders or multiple files.

1. A complete diagram of your ALU design, you can use any CAD tools to draw your logic. Make sure all inputs and outputs are outlined correctly and clearly. Indicate the width of each signal larger than one bit in your design.

3. Truth tables, K-maps, and equations, if used. Include your completed table 2.
4. An image of your simulation waveforms for part 3, please test all possible functions. 5. In your submission, please include any comments or suggestions.

Last Updated on September 21, 2018 by Essay Pro